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[PATCH] xtensa: Architecture support for Tensilica Xtensa Part 6
Chris Zankel authored 

The attached patches provides part 6 of an architecture implementation for the
Tensilica Xtensa CPU series.
Signed-off-by: default avatarChris Zankel <chris@zankel.net>
Signed-off-by: default avatarAndrew Morton <akpm@osdl.org>
Signed-off-by: default avatarLinus Torvalds <torvalds@osdl.org>
9a8fd558
Name Last commit Last update
..
a.out.h
atomic.h
bitops.h
bootparam.h
bug.h
bugs.h
byteorder.h
cache.h
cacheflush.h
checksum.h
coprocessor.h
cpumask.h
cputime.h
current.h
delay.h
div64.h
dma-mapping.h
dma.h
elf.h
errno.h
fcntl.h
fixmap.h
hardirq.h
hdreg.h
highmem.h
hw_irq.h
ide.h
io.h
ioctl.h
ioctls.h
ipc.h
ipcbuf.h
irq.h
kmap_types.h
linkage.h
local.h
mman.h
mmu.h
mmu_context.h
module.h
msgbuf.h
namei.h
page.h
page.h.n
param.h
pci-bridge.h
pci.h
percpu.h
pgalloc.h
pgtable.h
poll.h
posix_types.h
processor.h
ptrace.h
resource.h
rmap.h
rwsem.h
scatterlist.h
sections.h
segment.h
semaphore.h
sembuf.h
serial.h
setup.h
shmbuf.h
shmparam.h
sigcontext.h
siginfo.h
signal.h
smp.h
socket.h
sockios.h
spinlock.h
stat.h
statfs.h
string.h
system.h
termbits.h
termios.h
thread_info.h
timex.h
tlb.h
tlbflush.h
topology.h
types.h
uaccess.h
ucontext.h
unaligned.h
unistd.h
user.h
vga.h
xor.h