1. 05 Aug, 2005 4 commits
    • David Brownell's avatar
      [PATCH] USB: ehci: microframe handling fix · 7dedacf4
      David Brownell authored
      
      This patch has a one line oops fix, plus related cleanups.
      
       - The bugfix uses microframe scheduling data given to the hardware to
         test "is this a periodic QH", rather than testing for nonzero period.
         (Prevents an oops by providing the correct answer.)
      
       - The cleanup going along with the patch should make it clearer what's
         going on whenever those bitfields are accessed.
      
      The bug came about when, around January, two new kinds of EHCI interrupt
      scheduling operation were added, involving both the high speed (24 KBytes
      per millisec) and low/full speed (1-64 bytes per millisec) microframe
      scheduling.  A driver for the Edirol UA-1000 Audio Capture Unit ran into
      the oops; it used one of the newly supported high speed modes.
      Signed-off-by: default avatarDavid Brownell <dbrownell@users.sourceforge.net>
      Signed-off-by: default avatarAndrew Morton <akpm@osdl.org>
      Signed-off-by: default avatarGreg Kroah-Hartman <gregkh@suse.de>
      Signed-off-by: default avatarLinus Torvalds <torvalds@osdl.org>
      7dedacf4
    • Pete Zaitcev's avatar
      [PATCH] USB: ub documentation update · 003ba515
      Pete Zaitcev authored
      The patch which went in was correct, but not quite what I had in mind.
      Here is a patch to update that a little bit. Original patch is at:
       http://www.kernel.org/git/?p=linux/kernel/git/torvalds/linux-2.6.git;a=commit;h=4749f32da939d4e4160541b2cadc22492bb507ec
      
      Signed-off-by: default avatarPete Zaitcev <zaitcev@redhat.com>
      Signed-off-by: default avatarGreg Kroah-Hartman <gregkh@suse.de>
      Signed-off-by: default avatarLinus Torvalds <torvalds@osdl.org>
      003ba515
    • Dominik Brodowski's avatar
      [PATCH] pci and yenta: pcibios_bus_to_resource · 43c34735
      Dominik Brodowski authored
      
      In yenta_socket, we default to using the resource setting of the CardBus
      bridge.  However, this is a PCI-bus-centric view of resources and thus needs
      to be converted to generic resources first.  Therefore, add a call to
      pcibios_bus_to_resource() call in between.  This function is a mere wrapper on
      x86 and friends, however on some others it already exists, is added in this
      patch (alpha, arm, ppc, ppc64) or still needs to be provided (parisc -- where
      is its pcibios_resource_to_bus() ?).
      Signed-off-by: default avatarDominik Brodowski <linux@dominikbrodowski.net>
      Signed-off-by: default avatarAndrew Morton <akpm@osdl.org>
      Signed-off-by: default avatarGreg Kroah-Hartman <gregkh@suse.de>
      Signed-off-by: default avatarLinus Torvalds <torvalds@osdl.org>
      43c34735
    • John W. Linville's avatar
      [PATCH] PCI: restore BAR values after D3hot->D0 for devices that need it · fec59a71
      John W. Linville authored
      
      Some PCI devices (e.g. 3c905B, 3c556B) lose all configuration
      (including BARs) when transitioning from D3hot->D0.  This leaves such
      a device in an inaccessible state.  The patch below causes the BARs
      to be restored when enabling such a device, so that its driver will
      be able to access it.
      
      The patch also adds pci_restore_bars as a new global symbol, and adds a
      correpsonding EXPORT_SYMBOL_GPL for that.
      
      Some firmware (e.g. Thinkpad T21) leaves devices in D3hot after a
      (re)boot.  Most drivers call pci_enable_device very early, so devices
      left in D3hot that lose configuration during the D3hot->D0 transition
      will be inaccessible to their drivers.
      
      Drivers could be modified to account for this, but it would
      be difficult to know which drivers need modification.  This is
      especially true since often many devices are covered by the same
      driver.  It likely would be necessary to replicate code across dozens
      of drivers.
      
      The patch below should trigger only when transitioning from D3hot->D0
      (or at boot), and only for devices that have the "no soft reset" bit
      cleared in the PM control register.  I believe it is safe to include
      this patch as part of the PCI infrastructure.
      
      The cleanest implementation of pci_restore_bars was to call
      pci_update_resource.  Unfortunately, that does not currently exist
      for the sparc64 architecture.  The patch below includes a null
      implemenation of pci_update_resource for sparc64.
      
      Some have expressed interest in making general use of the the
      pci_restore_bars function, so that has been exported to GPL licensed
      modules.
      Signed-off-by: default avatarJohn W. Linville <linville@tuxdriver.com>
      Signed-off-by: default avatarGreg Kroah-Hartman <gregkh@suse.de>
      Signed-off-by: default avatarLinus Torvalds <torvalds@osdl.org>
      fec59a71
  2. 04 Aug, 2005 36 commits